Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on a specimen such as a reticle and a wafer. Inspection processes have always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection processes become even more important to the successful manufacture of acceptable semiconductor devices. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Accordingly, much work in the inspection field has been devoted to designing inspection systems that can detect defects having sizes that were previously negligible. Typical inspection processes detect defects by comparing similar semiconductor device areas on a wafer. The differences detected between the two device areas can either be a defect, which can cause a device to function improperly, or a nuisance, which will not affect system operations. An integral phase of semiconductor wafer inspection involves optimizing the settings, commonly referred to as the “recipe,” of an inspection device so that it can accurately distinguish defects from nuisances. After potential defects are found by an inspection system, the wafer is typically transferred to a review tool for classification of the defects. However, classification of the defects requires optimizing the settings of the review tool, also referred to as a “recipe”, so that the review tool can adequately classify the potential defects or determine that the potential defects are nuisances or false defects.
In sum, analysis of the defects on a particular wafer lot requires setting up and optimizing a recipe for an inspection tool and setting up a different recipe for the review tool. Setting up two recipes for two different tools is time consuming and complex.
Inspection for many different types of defects has also become more important recently. For instance, in order to use inspection results to monitor and correct semiconductor fabrication processes, it is often necessary to know what types of defects are present on a wafer. In addition, since controlling every process involved in semiconductor manufacturing is desirable to attain the highest yield possible, it is desirable to have the capability to detect the different types of defects that may result from many different semiconductor processes. The different types of defects that are to be detected may vary dramatically in their characteristics. For example, defects that may be desirable to detect during a semiconductor manufacturing process may include thickness variations, particulate defects, scratches, pattern defects such as missing pattern features or incorrectly sized pattern features, and many others having such disparate characteristics.
Metrology processes are also used at various steps during a semiconductor manufacturing process to monitor and control the process. Metrology processes are different than inspection processes in that, unlike inspection processes in which defects are detected on a wafer, metrology processes are used to measure one or more characteristics of the wafer that cannot be determined from currently used inspection tools. For example, metrology processes are used to measure one or more characteristics of a wafer such as a dimension (e.g., line width, thickness, etc.) of features formed on the wafer during a process such that the performance of the process can be determined from the one or more characteristics. In addition, if the one or more characteristics of the wafer are unacceptable (e.g., out of a predetermined range for the characteristic(s)), the measurements of the one or more characteristics of the wafer may be used to alter one or more parameters of the process such that additional wafers manufactured by the process have acceptable characteristic(s).
An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). The structures may take the form of gratings, and these gratings may be periodic. If the two layers or patterns are properly formed, then the structure on one layer or pattern tends to be aligned relative to the structure on the other layer or pattern. If the two layers or patterns are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. Overlay error is the misalignment between any of the patterns used at different stages of semiconductor integrated circuit manufacturing. Conventionally, understanding of the variation across die and wafer are limited to the fixed sampling and hence overlay error is detected only for the known selected sites.
There are, however, a number of disadvantages to using metrology processes and tools to measure one or more characteristics of a wafer for process monitoring and control applications. For example, most metrology tools are relatively slow, particularly compared to inspection systems. Therefore, metrology processes are often performed at one location or a limited number of locations on the wafer such that metrology results may be acquired in a relatively expedient manner. However, many processes used to manufacture semiconductor devices produce wafers that have characteristic(s) that vary across the surface of the wafers. As such, using metrology measurements performed at one location or a limited number of locations on a wafer may not provide sufficient information about the characteristic(s) of the wafers such that the process can be accurately monitored and controlled. Therefore, the sampling plan of the metrology process can significantly affect the meaningfulness and usefulness of the metrology results.
There are, however, a number of disadvantages to currently used metrology sampling plans. For instance, traditional metrology sampling approaches are based on fixed locations on the wafer, which may represent samples across the wafer or may be based on previously known problem areas on the wafer. Measurements may then be performed on given sites until the fixed sample plan is adjusted (e.g., manually). Therefore, one of the disadvantages of currently used metrology sampling plans is that the fixed sites that are sampled during metrology may not be sensitive to subtle variations in the process. For example, in the event that critical dimension (CD) varies in the areas on the wafer that the fixed sampling does not cover, an important excursion may be missed.
Accordingly, it may be desirable to provide a method and/or system which combine advanced defect inspection with overlay metrology in order to provide improved coverage and sampling efficiency in a process performed on a semiconductor wafer.